HPR29: HomePNA PHY TX Control (Register 29)
Table 61. HPR29: HomePNA PHY TX Control (Register 29)
Read/
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
Write
TX_CTRL
This value defines the duration of a transmit
pulse in OSC cycles (16.7 ns). This will
effectively determine the transmit spectrum of
the PHY.
15:8
TX_PULSE_WIDTH
R/W
04
04
This value defines the number of pulses that
will be driven onto the HRTXRX_N pin.
7:4
3:0
TX_PULSE_CYCLES_N
TX_PULSE_CYCLES_P
R/W
R/W
4
4
4
4
This value defines the number of pulses that
will be driven onto the HRTXRX_P pin.
HPR30: 1 Mbps HomePNA PHY Drive Level Control
Test Register (Register 30)
Table 62. HPR30: HomePNA PHY Drive Level Control Test Register (Register 30)
Read/
Write
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
15:12 RES
Reserved; Write = 0; Read = X
R
YX
Defines the drive level that will be utilized in the
High Power mode.
11:6
5:0
High Level Control
Low Level Control
R/W
15
09
Defines the drive level that will be utilized in the
Low Power mode.
R/W
HPR31: 1 Mbps HomePNA PHY Analog Control
Register (Register 31)
Table 63. HPR31: HomePNA PHY Analog Control Register (Register 31)
Read/
Default
Hex
Soft
Reset
Bits
Mnemonic
Description
Write
Global output slope adjustment. These bits
control the number of current sources enable
for transmit. Each bit represents a single
current source. Thus 10101 enables three
current sources as does 11100.
15:11 Level_Adjust
R/W
18
18
10:8
7
Reserved
Reserved; Write = 0
R/W
R/W
R/W
0
0
0
0
0
0
1 = Link Status bit will be held valid
0 = Normal operation
Force_Link_Valid
Reserved
6:0
Reserved; Write = 0
Note: 1. Writes to these bits will cause undefined functionality.
Am79C978
187
AMD [ AMD ]
