欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ AMD ]
 浏览型号AM79C978KC/W的Datasheet PDF文件第180页浏览型号AM79C978KC/W的Datasheet PDF文件第181页浏览型号AM79C978KC/W的Datasheet PDF文件第182页浏览型号AM79C978KC/W的Datasheet PDF文件第183页浏览型号AM79C978KC/W的Datasheet PDF文件第185页浏览型号AM79C978KC/W的Datasheet PDF文件第186页浏览型号AM79C978KC/W的Datasheet PDF文件第187页浏览型号AM79C978KC/W的Datasheet PDF文件第188页  
HPR20 and HPR21: HomePNA PHY RxCOMM  
(Registers 20 and 21)  
Table 53. HPR20 and HPR21: HomePNA PHY RxCOMM (Registers 20 and 21)  
Read/  
Write  
Default  
Hex  
Soft  
Reset  
Hex  
Mnemonic  
Description  
The 32-bit preamble received on the  
HomePNA PHY. Register 14 contains the high  
word and Register 15 the low word.  
14-15  
PHY_RX_COMM (4)  
R
All 0s  
All 0s  
The 32-bit received data field to be used for out-of-  
band communication between PHY management enti-  
ties. No protocol for out-of-band management has  
been defined. Accessing the low word of the register is  
sufficient to ensure that subsequently received packets  
will not over-write the register contents. A non-null re-  
ceived PCOM will set the RxPCOM Valid bit of the  
Event Status Register (Register HPR26). Accessing  
the high word of the register clears this bit and allows  
over-writing of the register by subsequent received  
packets.  
HPR22: HomePNA PHY AID (Register 22)  
Table 54. HPR22: HomePNA PHY AID (Register 22)  
Read/  
Write  
Default  
Hex  
Soft  
Reset  
Bits  
Mnemonic  
Description  
PHY_AID  
PHY_AID  
The Address ID of this PHY  
15:8  
7:0  
R/W  
R/W  
00  
00  
00  
00  
If PHY_Control Disable AID Negotiation is not  
set then writes to this bit will have no effect.  
An 8-bit counter that records the number of  
noise events detected. Overflows are held as  
FFh. Can be cleared by setting bit 6 of the  
control register.  
Noise Events  
The PHYs AID address is used for collision detection.  
Unless bit 7 of the CONTROL register is set, the PHY  
is assured to select a unique AID address. Addresses  
above EFh are reserved. Address FFh is defined to in-  
dicate a remote command.  
HPR23: HomePNA PHY Noise Control (Register 23)  
Table 55. HPR23: HomePNA PHY Noise Control (Register 23)  
Read/  
Default  
Hex  
Soft  
Reset  
Bits  
Mnemonic  
Description  
Write  
PHY_NOISE_CTRL1  
The minimum value of the NOISE  
measurement.  
15:8  
7:0  
Noise Floor  
R/W  
R/W  
03  
FF  
03  
FF  
The maximum value if the NOISE  
measurement. If it is exceeded, NOISE is reset  
to the FLOOR.  
Noise Ceiling  
184  
Am79C978