If DXMTFCS is set and
ADD_FCS is clear for a particular
frame, no FCS will be generated.
If ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0 will set
RXON bit (CSR0 bit 5) if STRT
(CSR0 bit 1) is asserted.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
CSR16: Initialization Block Address Lower
This bit was called DTCR in the
LANCE (Am7990) device.
Bit
Name
Description
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRL
This register is an alias of CSR1.
2
LOOP
Loopback Enable allows the
Am79C978 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MIIILP, various loopback modes
are defined as follows in Table
30.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
CSR17: Initialization Block Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADRH
This register is an alias of CSR2.
Table 30. Loopback Configuration
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set.
LOOP
INTL
MIIILP
Function
Normal Operation
Internal Loop
0
0
1
0
0
0
0
1
0
CSR18: Current Receive Buffer Address Lower
External Loop
Bit
Name
Description
Refer to Loopback Operation
section for more details.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
This bit is read/write accessible
only when either the STOP or the
SPND bit is set. LOOP is cleared
by H_RESET or S_RESET and
is unaffected by STOP.
15-0
CRBAL
Contains the lower 16 bits of the
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
1
DTX
Disable Transmit results in
Am79C978 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR19: Current Receive Buffer Address Upper
This bit is read/write accessible
only when either the STOP or the
SPND bit is set.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
0
DRX
Disable Receiver results in the
Am79C978 controller not access-
128
Am79C978
AMD [ AMD ]
