15-0
NRDAL
Contains the lower 16 bits of the
next receive descriptor address
pointer.
CSR30: Base Address of Transmit Ring Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
BADXL
Contains the lower 16 bits of the
base address of the Transmit
Ring.
CSR27: Next Receive Descriptor Address Upper
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRDAU
Contains the upper 16 bits of the
next receive descriptor address
pointer.
CSR31: Base Address of Transmit Ring Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
BADXU
Contains the upper 16 bits of the
base address of the Transmit
Ring.
CSR28: Current Receive Descriptor Address Lower
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRDAL
Contains the lower 16 bits of the
current receive descriptor ad-
dress pointer.
CSR32: Next Transmit Descriptor Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
NXDAL
Contains the lower 16 bits of the
next transmit descriptor address
pointer.
CSR29: Current Receive Descriptor Address Upper
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CRDAU
Contains the upper 16 bits of the
current receive descriptor ad-
dress pointer.
CSR33: Next Transmit Descriptor Address Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
NXDAU
Contains the upper 16 bits of the
next transmit descriptor address
pointer.
130
Am79C978
AMD [ AMD ]
