15-0
CRBAU
Contains the upper 16 bits of the
current receive buffer address at
which the Am79C978 controller
will store incoming frame data.
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR23: Next Receive Buffer Address Upper
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBAU
Contains the upper 16 bits of the
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
CSR20: Current Transmit Buffer Address Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
15-0
CXBAL
Contains the lower 16 bits of the
current transmit buffer address
from which the Am79C978 con-
troller is transmitting.
CSR24: Base Address of Receive Ring Lower
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADRL
Contains the lower 16 bits of the
base address of the Receive
Ring.
CSR21: Current Transmit Buffer Address Upper
Bit
Name
Description
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
CXBAU
Contains the upper 16 bits of the
current transmit buffer address
from which the Am79C978 con-
troller is transmitting.
CSR25: Base Address of Receive Ring Upper
Bit
Name
Description
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BADRU
Contains the upper 16 bits of the
base address of the Receive
Ring.
CSR22: Next Receive Buffer Address Lower
Bit
Name
Description
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
NRBAL
Contains the lower 16 bits of the
next receive buffer address to
which the Am79C978 controller
will store incoming frame data.
CSR26: Next Receive Descriptor Address Lower
Bit
Name
Description
These bits are read/write acces-
sible only when either the STOP
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
Am79C978
129
AMD [ AMD ]
