CSR11: Logical Address Filter 3
Bit
Name
Description
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PADR[31:16] Physical
Address
Register,
PADR[31:16]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
15-0 LADRF[63:48] Logical
Address
Filter,
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
CSR14: Physical Address Register 2
31-16 RES
Note: Bits 15-0 in this register are programmable
through the EEPROM.
15-0
PADR[15:0] Physical
Address
Register,
Bit
Name
Description
PADR[15:0]. The contents of this
register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 PADR[47:32] Physical
Address
Register,
PADR[47:32]. The contents of
this register are loaded from the
EEPROM after H_RESET or by
an EEPROM read command
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
126
Am79C978
AMD [ AMD ]
