affected by S_RESET or setting
the STOP bit.
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
2
MCCIINTE PHY Management Command
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate man-
agement frames. For instance,
when MCCIINTE is set to 1 and
the Auto-Poll state machine gen-
erates a management frame, the
MCCIINT will set the INTR bit
upon completion of the manage-
ment frame regardless of the
comparison outcome.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR9: Logical Address Filter 1
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
This bit is always read/write ac-
cessible. MCCIINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
15-0 LADRF[31:16] Logical Address Filter, LADRF-
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
1
MIIPDTINT PHY Detect Transition Interrupt.
The PHY Detect Transition Inter-
rupt is set by the Am79C978 con-
troller whenever the MIIPD bit
(BCR32, bit 14) transitions from 0
to 1 or vice versa.
These bits are These bits are
read/write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
This bit is always read/write ac-
cessible. MIIPDTINT is cleared
by the host by writing a 1. Writing
a 0 has no effect. MIIPDTINT is
cleared by H_RESET and is not
affected by S_RESET or setting
the STOP bit.
CSR10: Logical Address Filter 2
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
0
MIIPDTINTE PHY Detect Transition Interrupt
Enable. If MIIPDTINTE is set to 1,
the MIIPDTINT bit will be able to
set the INTR bit.
15-0 LADRF[47:32] Logical
Address
Filter,
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
This bit is always read/write ac-
cessible. MIIPDTINTE is set to 0
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
These bit are read/write accessi-
ble only when either the STOP or
the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR8: Logical Address Filter 0
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 LADRF[15:0] Logical Address Filter, LADRF-
[15:0]. The content of this register
Am79C978
125
AMD [ AMD ]
