15-12 RES
Reserved locations. Read and
written as zeros.
CSR43: Current Transmit Status
Bit
Name
Description
11-0
CRBC
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD1 of the current re-
ceive descriptor.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 CXST
Current Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the current transmit de-
scriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR41: Current Receive Status
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
CSR44: Next Receive Byte Count
Bit
Name
Description
15-0
CRST
Current Receive Status. This
field is a copy of bits 31-16 of
RMD1 of the current receive de-
scriptor.
31-16 RES
15-12 RES
11-0 NRBC
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD1 of the next receive de-
scriptor.
CSR42: Current Transmit Byte Count
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
Bit
Name
Description
31-16 RES
15-12 RES
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
CSR45: Next Receive Status
Bit
Name
Description
11-0
CXBC
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the current trans-
mit descriptor.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0 NRST
Next Receive Status. This field is
a copy of bits 31-16 of RMD1 of
the next receive descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR46: Transmit Poll Time Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
132
Am79C978
AMD [ AMD ]
