from where it had left, when it en-
tered the suspend mode.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
This bit is always read/write ac-
cessible. SPND is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
15 FASTSPNDE Fast Suspend Enable. When
FASTSPNDE is set to 1, the
Am79C978 controller performs a
fast suspend whenever the
SPND bit is set.
CSR6: RX/TX Descriptor Table Length
Bit
Name
Description
When a fast suspend is request-
ed, the Am79C978 controller per-
forms a quick entry into the
suspend mode. At the time the
SPND bit is set, the Am79C978
controller will complete the DMA
process of any transmit and/or re-
ceive packet that had already be-
gun DMA activity. In addition, any
transmit packet that had started
transmission will be fully transmit-
ted, and any receive packet that
had begun reception will be fully
received. However, no additional
packets will be transmitted or re-
ceived and no additional transmit
or receive DMA activity will begin.
Hence, the Am79C978 controller
may enter the suspend mode
with transmit and/or receive
packets still in the FIFOs or the
SRAM.
31-16 RES
15-12 TLEN
Reserved locations. Written as
zeros and read as undefined.
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during the Am79C978 controller
initialization. This field is written
during the Am79C978 initializa-
tion routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
TLEN is only defined after initial-
ization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
11-8
RLEN
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block during
Am79C978 controller initializa-
tion. This field is written during
the Am79C978 initialization rou-
tine.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C978
controller may take longer before
entering the suspend mode. At
the time the SPND bit is set, the
Am79C978 controller will com-
plete the DMA process of a trans-
mit packet if it had already begun,
and the Am79C978 controller will
completely receive a receive
packet if it had already begun.
Additionally, all transmit packets
stored in the transmit FIFOs and
the transmit buffer area in the
SRAM (if one is enabled) will be
transmitted and all receive pack-
ets stored in the receive FIFOs,
and the receive buffer area in the
SRAM (if one is enabled) will be
transferred into system memory.
Since the FIFO and SRAM con-
tents are flushed, it may take
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
RLEN is only defined after initial-
ization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
7-0
RES
Reserved locations. Read as 0s.
Write operations are ignored.
CSR7: Extended Control and Interrupt 2
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
much
longer
before
the
Am79C978 controller enters the
122
Am79C978
AMD [ AMD ]
