AMD
P R E L I M I N A R Y
is deasserted when the RESET pin is issued or the CRC
reset bit is set to 1 (SIR0); when the TXS bit is set to 1
(TIR8) or the RXS bit is set to 1 (TIR16); when TXRES
bit set to 1 (TIR8), or the RXRES bit is set to 1 (TIR16), or
the SRES bit is set to 1 (TIR0).
PLL is used for clock recovery, then the RXDATA input
will expect valid data at rising edges of the RXCIN input.
External versus internal PLL use is determined through
the setting of the ECLK bit in TCR2.
RXPE
Receiver Power Enable
HFCLK
High Frequency Clock
Output
Output
RXPE isanactivelowoutputthatisusedtopowerupthe
receive section of the transceiver. This pin is directly
controllable through a TAI register and is also program-
mable as an I/O with read capability.
HFCLK provides a reference clock for a transceiver syn-
thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one-half the clock rate of the CLKIN sig-
nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. HFCLK will be
LOW whenever the HFPE signal is inactive.
TXCMD
Transmit Command
Output
TXCMD is an active low output that is used to enable the
transceiver’s transmission onto the medium. When
TXCMD is low, the transceiver should enable its trans-
mission function and disable its receive function. When
TXCMD is high, the transceiver should disable its
transmission function and return to receive functionality.
This pin is directly controlled by the transmit state
machine in the TAI and the TXCMD bit of TIR11. The
timing of the TXCMD signal is programmable from a TAI
register. The polarity of this pin is programmable from a
TAI register.
HFPE
High Frequency Power Enable
Output
HFPE is an active low output that is used to power up the
high-frequency VCO section of the transceiver. This pin
is directly controllable through a TAI register and is also
programmable as an I/O with read capability.
LFCLK
Low Frequency Clock
Output
LFCLK provides a reference clock for a transceiver syn-
thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one half the clock rate of the CLKIN sig-
nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. LFCLK will be
LOW whenever the LFPE signal is inactive.
TXCMD
Transmit Command
Output
TXCMD is an active high output that is the logical in-
verse of the TXCMD output. This signal is only available
when the Am79C930 device is configured for the
PCMCIA mode of operation.
LFPE
TXDATA
Transmit Data
Low Frequency Power Enable
Output
Output
LFPE is an active low output that is used to power up the
low-frequency synthesizer section of the transceiver.
This pin is directly controllable through a TAI register
and is also programmable as an I/O with read capability.
TXDATA is an output that provides the serial bit stream
for transmission, including preamble, SFD, PHY
header, MAC header, data and FCS field, or a subset
thereof. Data delivered from the MAC to the transceiver
is valid at the rising edge of TXC and changes on the fall-
ing edge of TXC. The value of the TXDATA pin is pro-
grammable to 1, 0, or “last bit transmitted” whenever the
transmit circuit is idle and during ramp up and ramp
down of the transceiver’s transmit circuits.
LLOCKE
Synthesizer Lock
Input
LLOCKE is a general-purpose input that can be used to
convey a transceiver’s synthesizer lock signal to the
80188 embedded controller. The value of the LLOCKE
pin is readable at a register bit in the TIR register space.
TXDATA
Transmit Data
Output
RXDATA
TXDATA is an output that is the logical inverse of the
TXDATA output. This signal is only available when the
Am79C930 device is configured for the PCMCIA mode
of operation. The value of the TXDATA pin is 0 when-
ever the transmit circuit is idle and during ramp up and
ramp down of the transmitter.
Receive Data
Input
RXDATA is an input that accepts the serial bit stream for
reception, including Preamble, SFD, PHY header, MAC
header, Data and FCS field. The RXDATA input stream
is expected to be NRZ data. Clock recovery is per-
formed internal to the Am79C930 device. If an external
30
Am79C930
AMD [ AMD ]
