Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 87 also shows a 5 data phase Pass-Thru burst
write, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to accept data at
every BPCLK rising edge (every 30 ns in a 33 MHz
PCI system). In this example, the Add-On interface
accepts data every other clock. In the example, RD# is
asserted during the entire Add-On burst, but it can be
deasserted when PTRDY# is deasserted, the S5335
functions the same under both conditions.
Figure 87. Pass-Thru Burst Writes Controlled by PTRDY#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BPCLK
PTATN#
PTBURST#
PTNUM[1:0
]
0
1
PTWR
Fh
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
2Ch
0h
PT ADDRDATA1
DATA2
DATA3
XXXX DATA4
DATA5
DQ[31:0]
PTRDY#
PTADR#
DQ bus
Valid PCI data on
P
CI Burst Write completed
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