Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
The Add-On PTADR# input directly accesses the
Pass-Thru Address Register and drives the contents
onto the data bus (no BPCLK rising edge is required).
The byte enables, address, and SELECT# inputs are
ignored when PTADR# is asserted. RD# and WR#
must not be asserted when PTADR# is asserted.
The PCI bus cycle address is stored in the S5335 Pass-Thru Address Register.
Clock 0:
Clock 1:
The PCI address is recognized as an access to Pass-Thru region 1. PCI data is stored in the S5335 Pass-Thru
Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring.
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
Clock 2:
PTBURST#
Deasserted. The access has a single data phase.
PTNUM[1:0] 01. Indicates the PCI access is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru access is a write.
0h. Indicate the Pass-Thru access is 32-bits.
PTBE[3:0]#
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and
SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
SELECT#, byte enable, and the address inputs remain valid to read the Pass-Thru Data Register at offset 2Ch.
RD# is asserted to drive data register contents onto the DQ bus.
Clock 3:
Clock 4:
Clock 5:
If PTRDY# is asserted at the rising edge of clock 4, PTATN# is immediately deasserted and the Pass-Thru
access is completed at clock 5.
If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals),
PTRDY# can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 5 causes PTATN# to
be immediately deasserted.
PTATN# and PTBURST# deasserted at the rising edge of clock 6 indicates the Pass-Thru access is complete.
The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 7.
Clock 6:
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