Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 89 also shows a 5 data phase Pass-Thru burst
read, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to provide data
every BPCLK (every 30 ns in a 33 MHz PCI system).
In this example, the Add-On interface writes data
every other clock cycle. WR# is shown asserted during
the entire Add-On burst, but WR# can be deasserted
when PTRDY# is deasserted, the S5335 functions the
same under both conditions.
Figure 89. PCI Burst Read Controlled by PTRDY#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BPCLK
PTATN#
PTBURST#
PTNUM[1:0
PTWR
]
0
1
Fh
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
2Ch
0h
PT ADDR DATA1
DATA2
DATA3
DATA4
DATA5
DQ[31:0]
PTRDY#
PTADR#
to data register
Valid data written in
AMCC Confidential and Proprietary
DS1657 154
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
