Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI address information is stored in the S5335 Pass-Thru Address Register.
Clock 0:
Clock 1:
The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored
in the S5335 Pass-Thru Data Register. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is
occurring.
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
Clock 2:
PTBURST#
PTNUM[1:0]
PTWR
Asserted. The access has multiple data phases.
01. Indicates the PCI access is to Pass-Thru region 1.
Asserted. The Pass-Thru access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-able, address, and SELECT# inputs are changed
during this clock to select the Pass-Thru Data Register during clock cycle 3.
SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset
2Ch. RD# is asserted to drive data register contents onto the Add-On data bus.
Clock 3:
Clock 4:
Clock 5:
Clock 6:
Clock 7:
Clock 8:
Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5335. PTRDY# asserted at the rising
edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus.
Add-On logic is not fast enough to store DATA 2 by the rising edge of clock 5. PTRDY# deasserted at the ris-
ing edge of clock 5 extends the current data phase and DATA 2 remains driven on the Add-On bus.
Add-On logic uses the rising edge of clock 6 to store DATA 2 from the S5335. PTRDY# asserted at the rising
edge of clock 6 completes the current data phase. DATA 3 is driven on the Add-On bus.
Add-On logic is not fast enough to store DATA 3 by the rising edge of clock 7. PTRDY# deasserted at the ris-
ing edge of clock 7 extends the current data phase is and DATA 3 remains driven on the Add-On bus.
Add-On logic uses the rising edge of clock 8 to store DATA 3 from the S5335. PTRDY# asserted at the rising
edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing
PTATN# to be deasserted. Data on the Add-On bus is not valid.
Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 9. PTATN#
is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus.
Clock 9:
Add-On logic uses the rising edge of clock 10 to store DATA 4 from the S5335. PTRDY# asserted at the rising
edge of clock 10 completes the current data phase. DATA 5 is driven on the Add-On bus. PTBURST# is deas-
serted, indicating that on the PCI bus, the burst is complete except for the last data phase. Since the data is
double buffered, there may be one or two pieces of data available to the Add-On when PTBURST# becomes
inactive.
Clock 10:
This example shows the single data available case. If another piece of data was available, then PTATN#
would remain active instead of going inactive at clock 12.
Add-On logic is not fast enough to store DATA 5 by the rising edge of clock 11. PTRDY# deasserted at the ris-
ing edge of clock 11 extends the data phase and DATA 5 remains driven on the Add-On bus.
Clock 11:
Clock 12:
Clock 13:
Add-On logic uses the rising edge of clock 12 to store DATA 5 from the S5335. PTRDY# asserted at the rising
edge of clock 12 completes the final data phase.
PTATN# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5335
can accept new Pass-Thru accesses from the PCI bus at clock 14.
AMCC Confidential and Proprietary
DS1657 151
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
