Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI address information is stored in the S5335 Pass-Thru Address Register. The PCI address is recognized as
an access to Pass-Thru region 1. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring.
PTBURST# is asserted by the S5335, indicating the current Pass-Thru read is a burst.
Clock 0:
Clock 1:
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
PTBURST#
PTNUM[1:0]
PTWR
Deasserted, the S5335 does not yet recognize a PCI burst.
01. Indicates the PCI access is to Pass-Thru region 1.
Deasserted. The Pass-Thru access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed
during this clock to select the Pass-Thru Data Register during clock cycle 3.
SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset
2Ch.
Clock 2:
Clock 3:
Clock 4:
Clock 5:
WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5335. PTRDY# asserted at the rising edge
of clock 3 completes the current data phase.
WR# asserted at the rising edge of clock 4 writes DATA 2 into the S5335. PTRDY# asserted at the rising edge
of clock 4 completes the current data phase.
WR# asserted at the rising edge of clock 5 writes DATA 3 into the S5335. PTRDY# asserted at the rising edge
of clock 5 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to
be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough.
PTATN# remains deasserted at the rising edge of clock 6. The Add-On cannot write DATA 4 until PTATN# is
asserted. PTATN# is reasserted during the cycle, indicating the PCI initiator is no longer adding wait states.
Add-On logic continues to drive DATA 4 on the Add-On bus.
Clock 6:
Clock 7:
WR# asserted at the rising edge of clock 7 writes DATA 4 into the S5335. PTRDY# asserted at the rising edge
of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to
be deasserted. The PCI initiator is adding wait states.
PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 5 until PTATN# is
asserted. Add-On logic continues to drive DATA 5 on the Add-On bus.
Clock 8:
Clock 9:
PTATN# remains deasserted at the rising edge of clock 9. The Add-On cannot write DATA 5 until PTATN# is
asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during the cycle,
indicating the PCI initiator is done adding wait states.
WR# asserted at the rising edge of clock 10 writes DATA 5 into the S5335. PTRDY# asserted at the rising edge
of clock 10 completes the current data phase.
Clock 10:
Clock 11:
Clock 12:
WR# asserted at the rising edge of clock 11 writes DATA 6 into the S5335. PTRDY# asserted at the rising edge
of clock 11 completes the final data phase.
PTBURST# is deasserted at the rising edge of clock 12 indicating the Pass-Thru burst is complete. The S5335
can accept new Pass-Thru accesses from the PCI bus at clock 14. Any data written into the Pass-Thru data reg-
ister is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the rising edge of
clock 13).
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