Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
Figure 85. Single Cycle Pass-Thru Read with PTADR#
0
1
2
3
4
5
6
BPCLK
PTA TN#
PTBURST#
PTNUM[1:0]
PTWR
1
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
WR#
2Ch
0h
DQ[31:0]
PT ADDR
PT DA TA
PTRDY #
PTADR#
PCI Read cycle
completed
Data stored in Pass-Thru
data register
Figure 86. Pass-Thru Burst Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
BPCLK
PTATN#
PTBURST#
PTNUM[1:0]
PTWR
1
0h
PTBE[3:0]#
SELECT#
ADR[6:2]
BE[3:0]#
RD#
2Ch
0h
PT ADDRDATA1 DATA2 DATA3
XXXX DATA4
XXXX
DATA5 DATA6
XXXX
DQ[31:0]
PTRDY#
PTADR#
s
Valid PCI data on DQ bu
PCI Bu
rst Write completed
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