Revision 5.01 – November 30, 2005
S5335 – PCI Bus Controller, 3.3V
Data Sheet
PCI address information is stored in the S5335 Pass-Thru Address Register.
Clock 0:
Clock 1:
The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in
the S5335 Pass-Thru Data Register. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occur-
ring.
Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid
when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2.
Clock 2:
PTBURST#
Asserted. The access has a multiple data phases.
PTNUM[1:0] 01. Indicates the PCI access was to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru access is a write.
0h. Indicate the Pass-Thru access is 32-bits.
PTBE[3:0]#
The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and
SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3.
SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset
2Ch. RD# is asserted to drive data register contents onto the DQ bus.
Clock 3:
Clock 4:
Clock 5:
Clock 6:
Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5335. PTRDY# asserted at the rising
edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus.
Add-On logic uses the rising edge of clock 5 to store DATA 2 from the S5335. PTRDY# asserted at the rising
edge of clock 5 completes the current data phase. DATA 3 is driven on the Add-On bus.
Add-On logic uses the rising edge of clock 6 to store DATA 3 from the S5335. PTRDY# asserted at the rising
edge of clock 6 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing
PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot provide data quickly enough.
Data on the Add-On bus is not valid.
Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 7. PTATN# is
reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus.
Clock 7:
Clock 8:
Add-On logic uses the rising edge of clock 8 to store DATA 4 from the S5335. PTRDY# asserted at the rising
edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted again, causing
PTATN# to be deasserted. Data on the Add-On bus is not valid.
The PCI initiator is still adding wait states. Add-On logic cannot store data while PTATN# is deasserted.
Clock 9:
Because PTATN# remains deasserted, Add-On logic cannot read data at the rising edge of clock 10. PTATN# is
reasserted, indicating the PCI initiator is no longer adding wait states. DATA 5 is driven on the Add-On bus.
Clock 10:
Add-On logic uses the rising edge of clock 11 to store DATA 5 from the S5335. PTRDY# asserted at the rising
edge of clock 11 completes the current data phase. DATA 6 is driven on the Add-On bus.
Clock 11:
Clock 12:
Clock 13:
Add-On logic uses the rising edge of clock 12 to store DATA 6 from the S5335. PTRDY# asserted at the rising
edge of clock 12 completes the final data phase.
PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete.
The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 15.
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