S2046/S2050
GIGABIT ETHERNET CHIPSET
OTHER OPERATING MODES
The LOCKDETN output will go to inactive when no
data is present on the serial data inputs. When
LOCKDETN is in the inactive state, it indicates that
the PLL is locking to the local reference clock to main-
tain downstream clocking. When LOCKDETN is in
the active state, it indicates that the PLL is attempting
to lock to the incoming serial data. When serial data
is restored, the LOCKDETN output will stay in the
active state.
Loopback
The S2046 and S2050 have secondary high-speed I/O
to provide a local loopback path. The local loopback
configuration is shown in Figure 6. When OE1 is ac-
tive on the S2046, the high-speed data is passed out
the TLX/Y output. Operation of the TLX/Y output is
independent of the TX/Y output—data can be simul-
taneously output on both. With LPEN active on the
S2050, data on the RLX/Y input is passed through to
the parallel output. The local loopback path provides
the capability to perform off-line testing and system
diagnostics.
When lock is lost, the PLL will attempt to reacquire bit
synchronization, and will shift from the serial input
data to the reference clock so that the correct down-
stream clocking will be maintained. The PLL will
continuously shift between the reference clock and
the input data until input data has been restored. While
the PLL is locked to the reference clock, LOCKDETN
will remain active, with one exception: when all of the
following conditions are met, the LOCKDETN output
toggle between active and inactive, reflecting the in-
ternal PLL shift between reference clock and input
data: (a) LOCKREFN is not active; (b) the signal (or
noise) on the high-speed input is above the voltage
input sensitivity threshold; (c) the signal (or noise) on
the high-speed input varies from the reference clock
by more than 244 ppm, and (d) the signal (or noise)
on the high-speed input passes the run length crite-
ria. When these conditions are met, LOCKDETN will
toggle, and the RCLK/RCLKN outputs will also shift
slightly in frequency.
Operating Frequency Range
The S2046 and S2050 are optimized for operation at
the Gigabit Ethernet rate of 1250.0 Mbit/s. REFCLK
must be selected to be within 100 ppm of the desired
byte or word clock rate.
Test Modes
The TEST pin on the S2046 and the SYNCEN pin on
the S2050 provide a PLL bypass mode that can be
used for operating the digital area of the chip. In this
mode, clock signals are input through the reference
clock pins. This can be used for testing the device
during the manufacturing process or during an off-line
self-test. Sync detection is always enabled in test mode.
In any transfer of PLL control from the serial data to
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
The SYNCEN input on the S2050 must transition
through mid-state in less than five REFCLK periods
to insure that PLL bypass mode is not exerted. In
order to guarantee that the S2050 enters PLL bypass
mode, SYNCEN must be held in mid state for more
than seven REFCLK cycles.
March 29, 2000 / Revision B
6
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
