S2046/S2050
GIGABIT ETHERNET CHIPSET
Table 6. S2050 Pin Assignment and Descriptions
Level I/O
Pin # Description
Pin Name
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
TTL
O
45
43
42
40
38
37
35
34
32
31
29
28
25
24
22
21
18
17
15
14
Parallel output data. The width of the parallel data bus is
selected by the state of the DWS pin. Parallel data on this bus is
clocked out on the falling edge of RCLK. In 20-bit mode, D[0] is
the first bit received. In 10-bit mode, D[19:10] are used and
D[9:0] are driven to the high state. In 10-bit mode, D[10] is the
first bit received.
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOCKDETN
TTL
TTL
O
52
Lock Detect. Active Low. When active, LOCKDETN indicates
that the PLL is locked to the incoming data stream. When
inactive, it provides a system flag indicating that the PLL is
locked to the local reference clock.
LPEN
DWS
I
I
8
4
Loop Enable. Active High. When active, LPEN selects the
loopback differential serial input pins (RLX, RLY). When inactive,
LPEN selects RX and RY (normal operation).
Static
TTL
Data Width Select. The level on this pin selects the parallel data
bus width. When LOW, a 20-bit parallel bus width is selected,
and D[19:0] are active. When HIGH, a 10-bit parallel data bus is
selected, D[19:10] are active and D[9:0] will go HIGH. (See
Table 3.) A rising edge will reset the internal counters (used for
test).
RCLK
Diff.
TTL
O
I
49
48
Receive Clock. Parallel data is clocked out on the falling edge of
RCLK/RCLKN. After a sync word is detected, the period of the
current RCLK and RCLKN is stretched to align with the word
boundary. (See Table 3 for frequency.)
RCLKN
REFCLK
SYNC
PECL
TTL
2
Reference Clock. (Externally capacitively coupled.) A free-
running crystal-controlled reference clock for the PLL clock
multiplier. The frequency of REFCLK is set by the REFSEL pin.
(See Table 3.)
O
51
Sync (Framing) Detected. Active High. Upon detection of a valid
sync symbol (COMMA: 0011111XXX, positive running disparity),
this output goes active for one RCLK period. When SYNC is
active, the sync symbol is present on the parallel data bus bits
D[9:0] in 20-bit mode or D[19:10] in 10-bit mode. SYNC is gated
by SYNCEN.
RLX
RLY
Diff.
PECL
I
11
12
Receive Loopback Serial Inputs. (Externally capacitively
coupled.) The serial loopback data inputs. RLX is the positive
input, and RLY is the negative input.
March 29, 2000 / Revision B
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
