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S2050A/D 参数 Datasheet PDF下载

S2050A/D图片预览
型号: S2050A/D
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 19 页 / 158 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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S2046/S2050  
GIGABIT ETHERNET CHIPSET  
The SYNC output signal will go high whenever a  
COMMA character (0011111XXX, positive running dis-  
parity) is present on the parallel data outputs. The  
SYNC output signal will be low at all other times. This  
is true whether the S2050 is operating in 10-bit mode  
or in 20-bit mode.  
Figure 6. Interface Diagram  
Data In  
S2046  
Gigabit  
Ethernet  
Transmitter  
S2050  
Gigabit  
Ethernet  
Receiver  
Data Out  
RCLK  
TX/Y  
RX/Y  
OE0  
OE1  
TLX/Y  
RLX/Y  
LPEN  
Lock Detect  
The S2050 lock detect function indicates the state of  
the phase-locked loop (PLL) clock recovery unit. The  
PLL will indicate lock within 2.5µs after the start of  
receiving serial data inputs. If the serial data inputs  
have an instantaneous phase jump (from a serial  
switch, for example) the PLL will not indicate an out-  
of-lock state, but will recover the correct phase  
alignment. If a run length of 80-160 bits is exceeded  
the loop will declare loss of lock. Input data rate varia-  
tion (compared to REFCLK) can also cause loss of  
lock. Table 4 shows the response of the PLL loop  
circuit to input data rate variation. When lock is lost,  
the PLL will attempt to reacquire bit synchronization,  
and will shift from the serial input data to the refer-  
ence clock so that the correct frequency downstream  
clocking will be maintained.  
S2050  
Gigabit  
Ethernet  
Receiver  
S2046  
Gigabit  
Ethernet  
Transmitter  
LPEN  
Data Out  
RCLK  
RLX/Y  
RX/Y  
TLX/Y  
TX/Y  
Data In  
OE0, OE1  
Reference Clock Input  
The reference clock input must be supplied with a PECL  
single-ended AC coupled crystal clock source at ±100 PPM  
tolerance. See Table 3 for reference clock frequencies.  
Framing  
The S2050 provides SYNC character recognition and  
data word alignment of the TTL level compatible out-  
put data bus. During the data realignment process,  
the RCLKN phase will be adjusted, and the byte pre-  
vious to the comma character will be lost. No glitches  
will occur in the RCLKN signal due to the realign-  
ment. In systems where the SYNC detect function is  
undesired, a LOW on the SYNCEN input disables the  
SYNC function and the data will be “unframed”.  
Table 3. Receiver Operating Modes  
Reference  
Clock RCLK/RCLKN  
Word  
Width Frequency Frequency  
Data Rate  
(Mbits/sec)  
DWS REFSEL  
(Bits)  
(MHz)  
(MHz)  
62.50  
0
0
20  
62.50  
1250.0  
When framing is disabled by low SYNCEN, the S2050  
simply achieves bit synchronization and begins to de-  
liver parallel output data words whenever it has  
received full transmission words. No attempt is made  
to synchronize on any particular incoming character.  
62.5  
1
1
10  
125.0  
1250.0  
Table 4. Response of PLL Loop Circuit to Input Data Rate Variation  
Input Data Rate  
PLL  
PLL Present State  
Variation (compared  
to REFCLK)  
LOCKDETN  
New State  
0 - 244 ppm  
244 - 366 ppm  
>366 ppm  
H -->L  
Locked to input data  
Indeterminate  
Locked to  
REFCLK  
Indeterminate  
H
L
Locked to REF_CLK  
Locked to Input Data  
Indeterminate  
0 - 448 ppm  
448 - 732 ppm  
>732 ppm  
Locked to  
Input Data  
Indeterminate  
L -->H  
Locked to REF_CLK  
March 29, 2000 / Revision B  
5