S2046/S2050
GIGABIT ETHERNET CHIPSET
Table 5. S2046 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
TTL
I
50
49
48
47
44
43
42
41
38
37
36
35
31
30
29
28
25
24
23
22
Parallel Input Data. Data is clocked in on the rising edge of
REFCLK. In 20-bit mode, D[0] is transmitted first. In 10-bit
mode, D[10:19] are used, D[0:9] are ignored, and D[10] is
transmitted first.
D8
D7
D6
D5
D4
D3
D2
D1
D0
GND
DWS
GND
—
I
20
This pin must be connected to ground.
Static
TTL
19
Data Width Select. The level on this pin selects the parallel data
bus width. When LOW, a 20-bit parallel bus width is selected,
and D[0:19] are active. When HIGH, a 10-bit parallel data bus is
selected, D[10:19] are active and D[0:9] are not used. (See
Table 1).
OE1
Static
TTL
I
I
I
1
2
Active LOW Output Enable control for TLX/TLY outputs. When
inactive, TLX/TLY are disabled and remain in the logic low state.
OE0
Static
TTL
Active LOW Output Enable control for TX/TY outputs. When
inactive, TX/TY are disabled and remain in the logic low state.
REFCLK
PECL
16
Reference Clock. (Externally capacitively coupled.) A crystal-
controlled reference clock for the PLL clock multiplier. The
frequency of REFCLK is set by the REFSEL pin. (See Table 1.)
TCLK
Diff.
TTL
O
O
12
11
Transmit Clock. Differential TTL word rate clock true and
complement. See Table 1 for frequency.
TCLKN
TLX
TLY
Diff.
PECL
5
4
Transmit Serial Loopback Output. Differential PECL outputs that
are functionally equivalent to TX and TY. They are intended to
be used for loopback testing. Enabled by OE1. TLX is the
positive output, and TLY is the negative output.
TY
TX
Diff.
PECL
O
9
8
Transmit Serial Output. Differential PECL outputs that transmit
the serial data and drive 150Ω to ground. Enabled by OE0. TX
is the positive output, and TY is the negative output.
March 29, 2000 / Revision B
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
