S2046/S2050
GIGABIT ETHERNET CHIPSET
Description
Table 6. S2050 Pin Assignment and Descriptions (Continued)
Pin Name Level I/O
Pin #
RX
RY
Diff.
PECL
I
9
10
Receive Serial Input. (Externally capacitively coupled.) The
received serial data inputs. RX is the positive input, and RY is
the negative input.
SYNCEN
Static
TTL
I
3
Enable Sync (Framing). Active High. (Multilevel.) When Active,
enables SYNC output. When inactive data is treated as
unframed data. Holding this input at mid-level for more than
seven REFCLK cycles puts the device in PLL bypass (test)
mode.
REFSEL
Static
TTL
I
I
30
50
Reference Select. Input used to select the reference clock
frequency. (See Table 3.)
LOCK_REFN
TTL
Lock to Reference. Active Low. When active, forces the PLL to
lock to the REFCLK input and ignore the serial data inputs.
When inactive, PLL locks to the serial data input (normal
operation).
TTLVCC
TTLGND
+5V/
3.3V
–
–
19, 23,
36, 44
TTL Power Supply
GND
16, 20,
33, 41,
46
TTL Ground
ECLVCC
+3.3V
–
13, 27,
39
Core Power Supply
ECLVEE
AVCC
GND
+3.3V
GND
–
–
–
1, 26, 47 Core Ground
7
Analog Power Supply
Analog Ground
AVEE
5, 6
March 29, 2000 / Revision B
10
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
