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S2050A/D 参数 Datasheet PDF下载

S2050A/D图片预览
型号: S2050A/D
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 19 页 / 158 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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S2046/S2050  
GIGABIT ETHERNET CHIPSET  
Loopback  
S2046/S2050 OVERVIEW  
Local loopback is supported by the chipset, and pro-  
vides a capability for performing offline testing of the  
interface to ensure the integrity of the serial channel  
before enabling the transmission medium. It also al-  
lows for system diagnostics.  
The S2046 transmitter and S2050 receiver provide  
serialization and deserialization functions for block-  
encoded data to implement a Gigabit interface.  
Operation of the S2046/S2050 chips is straightfor-  
ward, as depicted in Figure 2. The sequence of  
operations is as follows:  
Figure 2. Interface Diagram  
Transmitter  
1. 10/20-bit parallel input  
2. Parallel-to-serial conversion  
3. Serial output  
Parallel  
Data Out  
Parallel  
Data In  
Serial  
Data  
RCLK  
TCLK  
TX/Y  
RX/Y  
S2046  
Transmitter  
S2050  
Receiver  
Receiver  
RCLKN  
SYNC  
TCLKN  
1. Clock and data recovery from serial input  
2. Serial-to-parallel conversion  
3. Frame detection  
Loopback  
TLX/Y  
RLX/Y  
REFCLK  
REFCLK  
Loopback  
4. 10/20-bit parallel output  
The 10/20-bit parallel data handled by the S2046 and  
S2050 devices should be from a DC-balanced en-  
coding scheme, such as the 8B/10B transmission  
code, in which information to be transmitted is en-  
coded 8 bits at a time into 10-bit transmission  
characters.  
LOCKDETN  
S2046 TRANSMITTER  
Architecture/Functional Description  
The S2046 transmitter accepts parallel input data and  
serializes it for transmission over fiber optic or coaxial  
cable media. The S2046 is fully compliant with the  
proposed 802.3z Specification, and supports the Gi-  
gabit Ethernet data rate of 1250 Mbps.  
Internal clocking and control functions are transpar-  
ent to the user. Details of data timing can be seen in  
Figure 5.  
A lock detect feature is provided on the receiver,  
which indicates that the PLL is locked (synchronized)  
to the data stream.  
Figure 3. S2046 Functional Block Diagram  
OE0  
OE1  
10  
10  
20  
2:1  
D
Q
D[19:0]  
10  
TX  
TY  
SHIFT  
REGISTER  
TEST  
DWS  
TLX  
CONTROL  
LOGIC  
TLY  
REFSEL  
REFCLK  
TCLK  
DIVIDE-BY-2  
PLL CLOCK  
MULTIPLIER  
TCLKN  
F = F X 10/20  
0
1
March 29, 2000 / Revision B  
2
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