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S2050A/D 参数 Datasheet PDF下载

S2050A/D图片预览
型号: S2050A/D
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 19 页 / 158 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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S2046/S2050  
GIGABIT ETHERNET CHIPSET  
The parallel input data word can be either 10 bits or  
20 bits wide, depending upon DWS pin selection. A  
block diagram showing the basic chip function is  
shown in Figure 3.  
10-Bit/20-Bit Mode  
The S2046 operates with either 10-bit or 20-bit paral-  
lel data inputs. Word width is selectable via the DWS  
pin. In 10-bit mode, D[10-19] are used and D[0-9] are  
ignored. See Table 2.  
Parallel/Serial Conversion  
The parallel-to-serial converter takes in 10-bit or 20-  
bit wide data from the input latch and converts it to a  
serial data stream. Parallel data is latched into the  
transmitter on the positive going edge of REFCLK.  
The data is then clocked synchronous to the clock  
synthesis unit serial clock into the serial output shift  
register. The shift register is clocked by the internally  
generated bit clock which is 10 or 20 times the  
REFCLK input frequency. The state of the serial out-  
puts is controlled by the output enable pins, OE0 and  
OE1. D[10] is transmitted first in 10-bit mode. D[0] is  
transmitted first in 20-bit mode. Table 2 shows the  
mapping of the parallel data to the 8B/10B codes.  
Reference Clock Input  
The reference clock input (REFCLK) must be supplied  
with a PECL single-ended AC coupled crystal clock  
source with 100 PPM tolerance to assure that the trans-  
mitted data meets the proposed 802.3z Specification  
frequency limits. The internal serial clock is frequency  
locked to the reference clock. Refer to Table 1 for  
reference clock frequencies.  
Table 1. Transmitter Operating Modes  
Reference  
Clock  
Width Frequency Frequency  
Word  
TCLK/TCLKN  
Data Rate  
(Mbps/sec)  
DWS REFSEL  
(Bits)  
(MHz)  
(MHz)  
62.5  
0
0
20  
62.5  
1250.0  
62.5  
1
1
10  
125.0  
1250.0  
Table 2. Data Mapping to 8B/10B Alphabetic Representation  
First Data Byte  
Second Data Byte  
10 11 12 13 14 15 16 17 18 19  
TX[0:19] or  
RX[0:19]  
0
a
1
b
2
c
3
d
4
e
5
f
6
g
7
h
8
i
9
j
8B/10B alphabetic  
representation  
a
b
c
d
e
f
g
h
i
j
First bit transmitted in 20-bit mode  
First bit transmitted in 10-bit mode  
Figure 4. S2050 Functional Block Diagram  
REFSEL  
LOCKREFN  
LOCKDETN  
REFCLK  
SHIFT  
D
RX  
REGISTER  
RY  
PLL CLOCK  
RECOVERY  
2:1  
RLX  
RLY  
20  
BITCLK  
D
Q
D(0:19)  
LPEN  
CONTROL  
SYNCEN  
LOGIC  
SYNC  
RCLK  
SYNC  
DETECT  
LOGIC  
DWS  
RCLKN  
DIVIDER  
March 29, 2000 / Revision B  
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