S2042/S2048
Other Operating Modes
Loopback
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Test Modes
The TEST pin on the S2042 and the SYNCEN pin on
the S2048 provide a PLL bypass mode that can be
used for operating the digital area of the chip. In this
mode, clock signals are input through the reference
clock pins. This can be used for testing the device
during the manufacturing process or during an off-
line self-test. Sync detection is always enabled in
test mode.
The SYCEN input on the S2048 must transition
through mid-state in less than five REFCLK periods
to ensure that PLL bypass mode is not entered. In
order to guarantee that the S2048 enters PLL by-
pass mode, SYNCEN must be held in mid-state for
more than seven REFCLK cycles.
The S2042 and S2048 have secondary high-speed
I/O to provide a local loopback path. The local loopback
configuration is shown in Figure 6. When OE1 is ac-
tive on the S2046, the high-speed data is passed out
the TLX/Y output. Operation of the TLX/Y output is
independent of the TX/Y output—data can be simul-
taneously output on both. With LPEN active on the
S2050, data on the RLX/Y input is selected and is
passed through to the parallel output. The local
loopback path provides the capability to perform
offline testing and system diagnostics.
Operating Frequency Range
The S2042 and S2048 are optimized for operation at
the Fibre Channel rates of 265.625, 531.25 and
1062.5 Mbps. Operation at other than Fibre Channel
rates is possible if the rate falls within
±10%
of the
nominal rate. REFCLK must be selected to be within
100 ppm of the desired byte or word clock rate.
6
April 10, 2000 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
