HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 6. Loopback Interface Diagram
Data In
OE0
OE1
S2042
Fibre
Channel
Transmitter
TX/Y
RX/Y
S2042/S2048
Table 3 . Receiver Operating Modes
Data Out
RCLK
LPEN
TLX/Y
RLX/Y
S2048
Fibre
Channel
Receiver
Reference
Word
Clock RCLK/RCLKN
Data Rate Width Frequency Frequency
RATESEL DWS REFSEL (Mbits/sec) (Bits)
(MHz)
(MHz)
0
0
1
1
Open
1
0
1
0
1
1
0
1
0
1
1062.5
1062.5
531.25
531.25
265.625
10
20
10
20
10
106.25
53.125
53.125
26.5625
26.5625
53.125
53.125
53.125
26.5625
26.5625
Local
Loopback
LPEN
Data Out
RCLK
Local
Loopback
S2048
Fibre
Channel
Receiver
RLX/Y
TLX/Y
RX/Y
TX/Y
S2042
Fibre
Channel
Transmitter
Data In
OE0
OE1
The SYNC output signal will go high whenever a
COMMA character (0011111XXX, positive running
disparity) is present on the parallel data outputs. The
SYNC output signal will be low at all other times.
This is true whether the S2048 is operating in 10-bit
mode or in 20-bit mode.
Lock Detect
The S2048 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 2.5
µs
after the start of
receiving serial data inputs. If a run length of 80-160
bits is exceeded, the loop will declare loss of lock.
Input data rate variation (compared to REF_CLK) can
also cause loss of lock. Table 4 shows the response
of the PLL loop circuit to input data rate variation.
When lock is lost, the PLL will attempt to re-aquire
bit synchronization, and will shift from the serial input
data to the reference clock so that the correct fre-
quency downstream clocking will be maintained.
The LOCKDETN output will go inactive when no data
is present on the serial data input. When LOCKDETN
is in the inactive state, it indicates that the PLL is
locking to the local reference clock to maintain down-
stream clocking. When LOCKDETN is in the active
state, it indicates that the PLL is attempting to lock to
the in coming serial data. When serial data is restored,
the LOCKDETN output will stay in the active state.
When lock is lost, the PLL will attemp to reaquire bit
synchronization, and will shift from the serial input data
to the reference clock so that the correct downstream
clocking will be maintained. The PLL will continuously
shift between the reference clock and the input data
until input data has been restored. While the PLL is
locked to the reference clock, LOCKDETN will remain
active, with one exception. When all of the following
conditions are met the LOCKDETN output will toggle
between active and inactive, reflecting the internal PLL
shift between reference clock and input data: (a)
LOCKREFN is not active, (b) the signal (or noise) on
the high-speed input is above the voltage input sensitiv-
ity threshold, (c) the signal (or noise) on the high-speed
input varies from the reference clock by more than 244
ppm, and (d) the signal (or noise) on the high-speed
input passes the run length criteria. When these condi-
tions are met, LOCKDETN will toggle and the RCLK/
RCLKN outputs will also shift slightly in frequency.
Table 4. Response of PLL Loop Circuit to Input Data Rate Variation
PLL Present State
Input Data Rate
Variation (compared
to REFCLK)
0 - 244 ppm
Locked to
REFCLK
244 - 366 ppm
>366 ppm
0 - 448 ppm
Locked to
Input Data
448 - 752 ppm
>752 ppm
LOCKDETN
PLL
New State
Locked to input data
Indeterminate
Locked to REF_CLK
Locked to Input Data
Indeterminate
Locked to REF_CLK
H -->L
Indeterminate
H
L
Indeterminate
L -->H
April 10, 2000 / Revision B
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
