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S2048A 参数 Datasheet PDF下载

S2048A图片预览
型号: S2048A
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, PQFP52, 10 X 10 MM, PLASTIC, QFP-52]
分类和应用: 电信电信集成电路
文件页数/大小: 23 页 / 172 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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®
DEVICE
SPECIFICATION
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
BiCMOS PECL CLOCK SERIAL INTERFACE CIRCUITS
HIGH PERFORMANCE GENERATOR
GENERAL DESCRIPTION
S2042/S2048
S2042/S2048
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards
• S2042 transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
• S2048 receiver PLL configured for clock and
data recovery
• 1062.5, 531.25 and 265.625 Mbps operation
• 10- or 20-bit parallel TTL compatible interface
• +3.3 V/+5 V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs
The S2042 and S2048 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062.5, 531.25 or 265.625 Mbps data rates
with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2048
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics.
Figure 1 shows a typical network configuration incor-
porating the chipset.
APPLICATIONS
High-speed data communications
• Supercomputer/Mainframe
• Workstation
• Switched networks
• Proprietary extended backplanes
• Mass storage devices/RAID drives
Figure 1. System Block Diagram
Fibre
Channel
Controller
S2042
TX
Optical
TX
Optical
RX
S2048
RX
S2048
RX
Optical
RX
Optical
TX
S2042
TX
Fibre
Channel
Controller
April 10, 2000 / Revision B
1