S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
The Destination device counts the number of data
words it receives from the HIPPI channel and uses
this number as the “seed” for the LLRC it computes
and checks against the received LLRC word.
DATA AND PARITY
32_DATA_+_4_PARITY (outputs) [DTOxx, PAROx]
These signals reflect what was received on the data
and parity lines of the HIPPI channel, resynchronized
to local clock. During a connection request
(CONNECT_REQUEST going high and remaining
high) the I-field is presented on these signals. The
LLRC is also presented to this interface after the last
word of each burst.
SYNC_ERROR (output) [SYNER]
This signal high indicates the loss of synchronization
with the HIPPI channel (overrun or underrun).
CHIP STATUS/CONTROL
MODE_SELECT_0, 1, and 2 (inputs) [MSELx]
Note: All parity errors are indicated but no recovery
action is taken by the Destination device. If there is a
parity error detected, then the data and bad parity
are passed through the Destination device.
There are several operating modes in which the
Destination device can be placed. Operational and
diagnostic modes are controlled by the data placed
on the MODE_SELECT bus. MODE_SELECT_2 is
the MSB and MODE_SELECT_0 is the LSB of this
bus. Mode value 0 (000) is to be used as the master
reset mode for all internal counters and state
machines and should be used for power-up
initialization. Mode value 4 (100) is the board test or
diagnostic mode. In this mode an internal “walking
zero” pattern generator will exercise all Host-side
TTL outputs and the parity error circuitry. The
SELECT_0, 1, 2 outputs will count through all eight
states allowing exercise of any external I-Field or
status registers driven by the Destination device.
Mode value 5 (101) is the normal functional mode for
the Destination device.
RX_PARITY_ERROR (output) [RPERR]
High indicates a detected parity error on a data word
received over the HIPPI channel. This is valid for
each word received; however, there may be a time
skew between this indication and the presentation of
data. See Figure 9 for details. The bad parity bit(s) is
presented with its associated data word.
During a connection request the data lines contain the
I-field. RX_PARITY_ERROR indication presented to
the host logic when a connection has not been
established tells the host that an I- field parity error has
been detected. The RX_PARITY_ERROR signal is
valid for every clock that I-field is presented. Bad
parity on the I-field will result in the chip raising
RX_PARITY_ERROR until one of the following things
happen:
25_MHz (INPUT) [25MHZ]
This signal provides the Destination device with a
25MHz TTL clock (also called local clock) and is
used to resynchronize the HIPPI channel clock and
data.
• The I-field changes (stabilizes) so that the
parity is good
50_MHz (INPUT) [50MHZ]
• The host logic accepts or rejects the connection
request based on I-field content and the state
of RX_PARITY_ERROR
This signal provides the Destination device with a 50
MHz TTL clock and is used for internal state
machine control, and for resynchronization. The
phase requirements between this clock and 25_MHz
are shown in Figure 9.
• The HIPPI channel source drops REQUEST
RX_LLRC_ERROR (output) [RLLER]
This signal high means that an LLRC error was
detected on a received burst. This signal is
presented to the host along with the LLRC following
the last word of the burst.
13
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
