Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
MDIO Bus and Address Register
Start of frame: Start of frame is indicated by 01
pattern.
S1220 uses a simple bi-directional two-wire bus for
efficient inter-IC control. This bus reads from and
writes into most of the S1220 control logic. The follow-
ing are some important features of MDIO bus:
Operation code: For read transaction, 10; For write
transaction, 01.
Device Address: The S1220 compares the five
address bits of device address to the latched address
bits. If they are equal, the S1220 proceeds with the
access. If they are not equal, the S1220 ignores the
access and does not drive the MDIO signal.
•
The S1220 has a unique address on the bus
and a simple master/slave relationship exists at
all times.
•
Only two bus lines are required; a Manage-
ment Data Input/Output line (MDIO) and a
Management Data Clock line (MDC).
Register address: This field is used to select the reg-
ister to be accessed.
The register mapping has been outlined below. The
serial port interface is based on the IEEE802.3u MII
Management Interface standard. Communication
occurs across two wires and is formatted in frames.
The two wires are clock (MDC) and data (MDIO).
There is no preamble required before a frame as
described in the IEEE standard. At the rising edge of
RSTB, the S1220 loads the device address into a reg-
ister from the MII_ADDR[4:0] pins and uses it to
decode accesses to its registers. The MII_ADDR[4:0]
default is defined by the user. These address bits are
used to uniquely identify each S1220 device if multiple
S1220 devices are controlled by a single microproces-
sor. Because there are five address lines, 32 S1220
devices can be configured by a single microprocessor.
A frame is formatted as shown in Table 7.
Turnaround: The two bits between address field and
data field are used to avoid contention on the MDIO
during a read transaction. For a read transaction,
MDIO should be in tri-state for the first cycle of the
turnaround. The S1220 drives zero during the second
cycle of the turnaround. For a write transaction, the
system should drive one during the first cycle of the
turnaround and zero during the second cycle of the
turnaround.
Data field: Bits 15:8 are always zero. Bits 7:0 contain
the contents of the selected register. On reads,
reserved register bits will be defined and should not be
modified. The first bit transmitted is bit 15.
Idle condition: A final clock puts MDIO back in an idle
state (MDIO is tri-stated and pulled-up).
Table 7. Serial Port Frame Format
START OF OPERATION
DEVICE
ADDRESS
REGISTER
ADDRESS
TURN
AROUND
FRAME
CODE
DATA
IDLE
Read
Write
01
10
AAAAA
AAAAA
RRRRR
Z0
10
00000000DDDDDDDD
00000000DDDDDDDD
Z
Z
01
01
RRRRR
12
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