Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
smoothed by an internal loop filter. The output of the
loop filter controls the frequency of the Voltage Con-
trolled Oscillator (VCO), which generates the
recovered clock.
S1220 FUNCTIONAL DESCRIPTION
Clock Recovery
The Clock Recovery PLL, as shown in the block dia-
gram in Figure 2, generates a clock that is at the same
frequency as the incoming data bit rate at the SER-
DATI input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
Table 5. Reference Clock Frequency Select
Reference Frequency
(MHz)
19.44
77.76
155.52
REFSEL1
REFSEL0
The phase relationship between the edge transitions
of the data and those of the generated clock are com-
pared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are
0
0
1
0
1
x
Table 6. Rate Select Logic
Channel i MODE
Channel 0
Channel 1
Channel 2
Channel 3
TSCLK
i=0,1,2,3
RATESEL 0,1,2,3 = 0000
RATESEL 0,1,2,3 = 0001
RATESEL 0,1,2,3 = 0010
RATESEL 0,1,2,3 = 0011
RATESEL 0,1,2,3 = 0100
RATESEL 0,1,2,3 = 0101
RATESEL 0,1,2,3 = 0110
RATESEL 0,1,2,3 = 0111
RATESEL 0,1,2,3 = 1000
RATESEL 0,1,2,3 = 1001
RATESEL 0,1,2,3 = 1010
RATESEL 0,1,2,3 = 1011
RATESEL 0,1,2,3 = 1100
RATESEL 0,1,2,3 = 1101
RATESEL 0,1,2,3 = 1110
RATESEL 0,1,2,3 = 1111
OC-3
OC-3
OC-3
OC-3
OC-3
OC-3
OC-3
OC-12
OC-3
OC-3
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-3
OC-3
OC-12
OC-12
OC-3
OC-3
OC-3
OC-12
OC-3
OC-3
OC-12
OC-12
OC-12
OC-12
OC-3
OC-3
OC-3
OC-12
OC-3
OC-3
OC-12
OC-12
OC-3
OC-3
OC-12
OC-3
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-12
OC-3
OC-3
OC-12
OC-3
OC-3
OC-12
OC-12
OC-3
OC-3
OC-12
OC-3
OC-12
OC-12
OC-12
OC-12
OC-3
OC-12
OC-3
OC-12
OC-12
OC-12
Note: In Mix (OC-3/OC12) Mode the TSCLK rate is always OC-12 (622.08 MHz).
10
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