Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Lock Detect
Signal Detect Polarity (SDPOL)
The S1220 contains a lock detect circuit which moni-
tors serial data input bit rate for rates at or around the
REFCLK input frequency. If the received serial data
rate fails the bit rate test, the PLL will be forced to lock
to the REFCLK input. This will maintain the correct fre-
quency of the receive output clock under loss-of-lock
or loss-of-signal conditions. The PLL out-of-lock limits
with respect to the REFCLK frequency are defined in
Table 14 under the “Frequency difference at which the
receive PLL goes out of lock” parameter. The LOCK-
DET status output indicates the lock-to-data state of
the PLL relative to the REFCLK frequency. Once
asserted, the LOCKDET output will remain active
(logic 1) up to an offset input bit rate of the limits stated
in Table 14. Beyond the specified PLL locked-to-data
limits the LOCKDET status indicator produces a falling
edge (High to Low transition). The LOCKDET output,
as a true indicator of the PLL locked-to-data condition,
is valid when steady-state logic 1 and upon its falling
edge “out-of-lock” transition. For input data rates
beyond the stated ± ppm of REFCLK, the action of this
status indicator becomes indeterminate. The lock
detect circuit will poll the input data stream in an
attempt to reacquire lock-to-data. Once the lock detec-
tor hardware has determined, relative to REFCLK, that
the input data stream is within the “Frequency differ-
ence at which the receive PLL goes into lock”
parameter limit, the LOCKDET indicator will again
become valid to indicate a PLL locked-to-data
condition.
The signal detect polarity is an input signal that will set
the SD inputs as either active High or active Low. Set-
ting this pin Low will set the SD inputs as active High.
Setting this pin High will set the SD inputs as active
Low. This input can be accessed through the MDIO
bus register in MII mode and via SDPOL pin in Non-
MII Mode.
PLEB Loop Enable
Loop serial input to the serial output by using the CSU
clock instead of CDR clock for the SERDATA outputs.
This loop selection is only accessible through the MDIO bus
register (MII Mode).
Note: In MII, LLEB mode requires that both LLEB and
PLEB are enabled for proper power consumption.
Initialization Sequence
MII Mode:
•
•
•
•
Power on
Supply REFCLK
Set REFSEL[1:0] Bits
Reset Cores (Toggle cores OFF/ON, all chan-
nels)
Non-MII Mode:
•
•
•
•
Power on
Supply REFCLK
Set REFSEL[1:0] Pins
Reset Device
Note: Loss of REFCLK requires core reset.
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