Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
PIN ASSIGNMENT AND DESCRIPTIONS
Table 9. S1220 Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin #
Description
Inputs
REFCLKP
REFCLKN
Diff.
LVPECL or
LVDS
I
P8
P7
Reference Clock. 19.44 MHz, 77.76 MHz or 155.52 MHz. This refer-
ence clock is used to establish the initial operating frequency of the
clock recovery PLL and also used as a frequency reference for the
internal bit clock in the absence of serial data or during reset in clock
recovery mode.
SERDATIP0
SERDATIN0
SERDATIP1
SERDATIN1
SERDATIP2
SERDATIN2
SERDATIP3
SERDATIN3
Diff.
LVPECL
or LVDS
I
I/O
I
G1
G2
J1
Serial data input. A clock is recovered from transitions on these
inputs. The clock is used to sample and regenerate this signal.
J2
When any input is unused or data is invalid the associated input
channel should be kept in a known state by either being powered
down, locked to reference, or disabled with the associated signal
detect.
J14
J13
G14
G13
SD0
SD1
SD2
SD3
LVPECL
Compatible
with
LVCMOS &
most
G3
F3
F12
G12
Signal Detect. SDPOL sets the active polarity. When SD is inactive,
the data on the Serial Data Input (SERDATIP/N) pins will be inter-
nally forced to a constant zero, LOCKDET forced low, and the PLL
forced to lock to the REFCLK input. When SD is active, data on the
SERDATIP/N pins will be processed normally.
In MII Mode these input pins could be used for status outputs if the
appropriate register value is changed from zero to one (Internal use
only).
LVTTL
RATESEL0
RATESEL1
RATESEL2
RATESEL3
3.3 V/2.5 V
LVCMOS
Pull up
A6
A10
A9
Rate Select. This input selects the data rate for each of the 4 chan-
nels. Set High to select OC-12 (622.08 Mbps). Set Low to select
OC-3 (155.54 Mbps). CSU rate is OC-12 if any of the channels is in
OC-12.
A5
In MII mode these functions are controlled via MII register bits.
Tie these pins to VSS in MII mode.
REFSEL0
REFSEL1
3.3 V/2.5 V
LVCMOS
I
E14
B8
Reference Select. This input selects the frequency of the
REFCLKP/N.
I/O
REFSEL[1:0] = 1x selects 155.52 MHz
REFSEL[1:0] = 01 selects 77.76 MHz
Pull down
(REFSEL0)
REFSEL[1:0] = 00 selects 19.44 MHz
These controls are used only for non-MII mode. In MII mode these
functions are controlled via MII register bits. In MII Mode, the
REFSEL0 pin is alternatively assigned to the MII_ADDR3 pin func-
tion.
RSTB
3.3 V/2.5 V
LVCMOS
I
I
E12
External Reset. Active Low.
MODE0
MODE1
3.3 V/2.5 V
LVCMOS
E1
E2
Sets operation mode:
Non-MII Mode = 11
MII Mode = 00
Test Mode = 10, For internal use only
Internal Mode = 01, For internal use only
MDC (MII Mode)
3.3 V/2.5 V
LVCMOS
I/O
K12
Management Data Clock (MII Interface Clock - only used in MII
Mode).
Tie this pin to VDDHIO in Non-MII mode.
14
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