Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 9. S1220 Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin #
Description
SERCLKOOFF
3.3 V/2.5 V
LVCMOS
Pull up
I
D2
Serial Clock Out Off. Disables the SERCLK outputs on all 4 channels
in Non-MII mode. Active High.
In MII mode this function is controlled by bits in the MII register file.
In MII Mode SERCLKOOFF pin is assigned for the MII_ADDR4 pin.
TSCLKOOFF
3.3 V/2.5 V
LVCMOS
Pull up
I
I
C12
Transmit Serial Clock Out Off. Active High. In Non-MII mode only.
In MII mode this function is controlled via a MII register bit.
Connect to VSS in MII mode to provide initial value to internal control
bit.
MII_ADDR0
MII_ADDR1
MII_ADDR2
MII_ADDR3
MII_ADDR4
3.3 V/2.5 V
LVCMOS
J3
D3
D14
E14
D2
MII address setting (used only for MII mode).
In non MII these pins have other functionality (COREOFFA, CORE-
OFFB, DCBIAS, REFSEL0 and SERCLKOOFF).
COREOFFA
COREOFFB
3.3 V/2.5 V
LVCMOS
I
J3
D3
COREOFFA/B give the option to power down the core of unused
channels in the S1220. When a channel is powered off, the clock and
Data outputs are also disabled for that channel.
The following configuration are available:
COREOFFA/COREOFFB = 00: all Cores on.
COREOFFA/COREOFFB = 10: Cores 0,1- on Core 3,2 off.
In MII mode core disabling is available via register bits.
In MII Mode COREOFFA and COREOFFB pins are alternatively
assigned to MII_ADDR0 and MII_ADDR1 pin functions, respectively.
DCBIAS
SDPOL
3.3 V/2.5 V
LVCMOS
Pull down
I
D14
H3
DCBIAS. Active High.
Enables the on chip resistor bias for external LVPECL driver. Using
this feature provides seamless connection without external compo-
nents. In MII mode this is controlled via a MII register bit.
In MII Mode, DCBIAS pin is alternatively assigned to the MII_ADDR2
pin function.
3.3 V/2.5 V
LVCMOS
I/O
Signal Detect Polarity.
The signal detect polarity is an input signal that will set the SD inputs
as either active High or active Low. Setting this pin Low will set the
SD inputs as active High. Setting this pin High will set the SD inputs
as active Low. This input can be accessed through the MDIO bus
register in MII mode and via SDPOL pin in Non-MII Mode.
Tie this pin to VSS in MII mode.
MDIO (MII Mode)
XLVDSPECLB
(Non-MII Mode)
3.3 V/2.5 V
LVCMOS
I/O
I/O
J12
B14
Management Data Input/Output (MII Interface Data - only used in MII
Mode).
In Non-MII Mode this pin is XLVDSPECLB, which controls CDR’s
output format. When high the output is LVDS. When low the output is
LVPECL.
CLVDSPECLB
3.3 V/2.5 V
LVCMOS
In Non-MII Mode this pin is CLVDSPECLB, which controls the CSU’s
TSCLK output format.
1 - LVDS Mode
0 - LVPECL Mode
In MII mode this function is controlled via MII register bit.
In MII mode this pin is the TXLOCK output pin, outputting LOCK con-
dition of the CSU PLL.
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