Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 10. S1220 Power and Ground Pin Assignments and Descriptions
Pin Name
VDDSD
VDD
Level
+3.3 V
+1.2 V
GND
I/O
Pin #
Description
Power 3.3 V
E3, F4,
B11, C6, E9, F5, F7, F10
Power 1.2 V, Digital CMOS Supply
Ground, Digital CMOS
VSS
A1, A2, A3, A13, A14, B1, B7, C4, C11, D1, E5, E7,
E10, F6, F9, F11
VSSD
VDDHIO
VDDI
GND
A7, A11, B3, B5, B9, B12, C2, C7, C10, C13, D5, E4,
E8, E11
Ground, LVCMOS I/O
2.5V/
+3.3 V
A4, A8, B2, B6, B10, B13, C1, C5, C8, C9, C14, D4,
D10, D11, D13, E6, F8
Power 2.5 V or 3.3 V, LVCMOS I/O
Power 1.2 V, Analog supply
Ground, Analog
+1.2 V
G4, G6, G8, G10, H4, H5, H11, H12, J4, J5, J11, K3,
K5, K6, K7, K8, K10, K11 L4, L6, L9
VSSI
GND
F1, F2, F13, F14, G5, G7, G9, G11, H1, H2, H13,
H14, K1, K2, K9, K13, K14, L7, L8, M6, M9, N7, N8
VSSIO
VDDH
GND
H7, H9, J6, J8, J10, K4, L3, L5, L12, N3, N6, N9, N12 Ground, Serial Output Ground
+2.5 V/
+3.3 V
H6, H8, H10, J7, J9, L1, L2, L10, L11, L13, L14, M3,
M12, N1, N2, N4, N5, N10, N11, N13, N14, P3, P6,
P9, P12
Power 2.5 V or 3.3 V
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DS2018
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