QT2022/32 - Data Sheet: DS3051
PHY_XS Vendor
Specific
Bit
Register 4.C002h
5:0
6
Reserved, RO
XGXS Rx rate adjust underflow 1, RO/LH
1 = underflow
linked to 1.9003h.6
XGXS Rx rate adjust overflow 1, RO/LH
1 = overflow
linked to 1.9003h.6
7
8
9
XGXS Tx rate adjust underflow 1, RO/LH
1 = underflow
linked to 1.9004.2
XGXS Tx rate adjust overflow 1, RO/LH
1 = overflow
linked to 1.9004.2
11:10
12
Reserved, RO
XGXS Rx Rate Inserted Idle Flag, RO/LH
XGXS Rx Rate Removed Idle Flag, RO/LH
XGXS Tx Rate Inserted Idle Flag, RO/LH
XGXS Tx Rate Removed Idle Flag, RO/LH
13
14
15
1. This bit is linked to an MDIO latched high diagnostic alarm register bit. A read of either register clears both.
PHY_XS Vendor Specific
Register 4.C003h
PHY_XS Vendor Specific
Register 4.C004h
Bit
3:0
XAUI Lane 0
XAUI Lane 0
Sync offset, RO
Align offset, RO
7:4
XAUI Lane 1
XAUI Lane 1
Sync offset, RO
Align offset, RO
11:8
XAUI Lane 2
XAUI Lane 2
Sync offset, RO
Align offset, RO
15:12
XAUI Lane 3
XAUI Lane 3
Sync offset, RO
Align offset, RO
180
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