QT2022/32 - Data Sheet: DS3051
PHY_XS Vendor Specific
AMCC Test Patterns
Control
PHY_XS Vendor Specific
AMCC Test Patterns
Programmable Value
Register 4.C011h
Bit
Register 4.C010h
0
1
2
3
4
Enable XAUI Lane 0 for AMCC Test Pattern
0 = Disable, Default
1 = Enable
AMCC Test Pattern
Programmable Value, RW
Enable XAUI Lane 1 for AMCC Test Pattern
0 = Disable, Default
1 = Enable
Enable XAUI Lane 2 for AMCC Test Pattern
0 = Disable, Default
1 = Enable
Enable XAUI Lane 3 for AMCC Test Pattern
0 = Disable, Default
1 = Enable
Select AMCC Test
Pattern on XAUI Lane 0
0 = Static, Default
1 = User Defined Value
5
6
7
Select AMCC Test
Pattern on XAUI Lane 1
0 = Static, Default
1 = User Defined Value
Select AMCC Test
Pattern on XAUI Lane 2
0 = Static, Default
1 = User Defined Value
Select AMCC Test
Pattern on XAUI Lane 3
0 = Static, Default
1 = User Defined Value
8
9
Reserved, RO
Reserved, RO
Reserved, RO
15:10
Reserved, RO
182
AppliedMicro - Confidential & Proprietary
Revision 5.11
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
