QT2022/32 - Data Sheet: DS3051
PHY_XS Identifier
PHY_XS Identifier
4.3
Bit
4.2
PHY_XS Identifier1, RO
1100_0010_0000_0000
15:0
PHY_XS Identifier, RO
0000_0000_0010_0101
1. The PHY_XS unique identifier is the AMCC identifier.
‘
PHY_XS Speed Ability
Register 4.4
PHY_XS Devices in Package
PHY_XS Devices in
Package Register 4.6
PHY_XS Status 2
Register 4.8
Bit
Register 4.5
0
1, PCS is capable of operat-
ing at 10 Gb/s, RO
0, Clause 22 registers not present in
package, RO
Reserved, RO
Reserved, RO
1
2
Reserved, RO
1, PMA/PMD present in package,
RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
1, WIS present in package
(QT2032), RO
0, WIS not present in package
(QT2022), RO
3
4
5
Reserved, RO
Reserved, RO
Reserved, RO
1, PCS present in package, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
1, PHY_XS present in package, RO
0, DTE_XS not present in package,
RO
6
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
7
8
9
Receive local fault1 2,RO/LH
1=fault condition
10
linked to 1.9003h.0
Transmit local fault3 2, RO/LH
1=fault condition
11
Reserved, RO
Reserved, RO
Reserved, RO
linked to 1.9004h.0
12
13
14
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
0=Device responding at this
address, RO
15
Reserved, RO
Reserved, RO
0, vendor specific device
not present in package,
RO
1=Device responding at this
address, RO
1. PHY_XS Receive Local fault condition = (xlock = XAUI pll locked), where xlock = 4.C000h.3
2. This bit is linked to an MDIO latched high diagnostic alarm register bit. When either register is read both bits will be cleared.
3. PHY_XS Transmit Local fault condition = (Lane deskew), where lane deskew = 4.24.12
176
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
