QT2022/32 - Data Sheet: DS3051
10G PHY XGXS
Lane Status
Register 4.24 (4.18h)
PHY_XS Test Control
register 4.25 (4.19h)
Bit
0
1
Lane 0 sync, RO
1=lane is in sync
Test Pattern Select, RW
bit 1 bit 0
1
1
0
0
1
0
1
reserved
Lane 1 sync, RO
1=lane is in sync
mixed speed
low speed
high speed
0
XGXS Receive Test Pattern Enable1, RW
0 = disable
1 = enable
2
3
Lane 2 sync, RO
1=lane is in sync
Lane 3 sync, RO
1=lane is in sync
Reserved, RO
4
5
6
7
8
9
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
10
11
12
PHY_XS loopback ability, RO
1 = capable of PHY_XS loopback
PHY_XS pattern testing ability, RO
1 = capable of PHY_XS pattern testing
Reserved, RO
Reserved, RO
XGXS transmit lanes aligned, RO
1= lanes aligned
13
14
15
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
1. XGXS test pattern precedence: test(4.25.2), PRBS(4.C000h.10), CJPAT(4.C000h.8), CRPAT(4.C000h.9).
Revision 5.11
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