QT2022/32 - Data Sheet: DS3051
PHY_XS Vendor
Specific
PHY_XS Vendor
Specific
Bit
Register 4.C000h
Register 4.C001h
6
7
8
xtxlock<2> = lane 2 lock, RO
1=lane 2 in lock
Reserved, RO
Reserved, RO
Reserved, RO
xtxock<3> = lane 3 lock, RO
1=lane 3 in lock
CJPAT Generator Enable 1, RW
0 = disable, default
1 = enable
CRPAT Generator Enable 1, RW
0 = disable, default
1 = enable
9
Reserved, RO
Reserved, RO
XAUI PRBS Generator Enable 1, RW
0 = Generator Disabled (default)
1 = Generator Enabled
10
11
12
13
14
15
XAUI PRBS Checker Enable, RW
0 = Checker Disabled (default)
1 = Checker Enabled
Reserved, RO
Reserved, RO
XAUI version, RO
Reserved, RO
Reserved, RO
TxXMONCV source
0 = lane 3 recovered clock (default)
1 = lane 3 recovered data (XCKGN VCO CV at TxXMONCV)
XAUI network loopback data override, RW
1=transmit data (default)
0=transmit idles
XAUI system loopback enable, RW
0= loopback disabled (default)
1= loopback enabled
XAUI system loopback data override, RW
1=transmit data
0=transmit all 1’s (default)
1. XGXS test pattern precedence: test(4.25.2), PRBS(4.C000h.10), CJPAT(4.C000h.8), CRPAT(4.C000h.9).
Revision 5.11
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