QT2022/32 - Data Sheet: DS3051
PHY_XS Vendor
PHY_XS Vendor
Specific
Bit
Specific
Register 4.C000h
Register 4.C001h
0
1
Transmit XGXS reset, RW
0=reset
1= not reset, default
Note: not self clearing
XAUI Lane 0 PRBS Error, RO/LH
1 = PRBS Error
Receive XGXS reset, RW
0=reset
XAUI Lane 0 PRBS Error, RO/LH
1 = PRBS Error
1= not reset, default
Note: not self clearing
2
3
4
5
Reserved, RO
XAUI Lane 0 PRBS Error, RO/LH
1 = PRBS Error
Receive path XAUI PLL locked xlock, RO
1=locked
XAUI Lane 0 PRBS Error, RO/LH
1 = PRBS Error
xtxlock<0> = lane 0 lock, RO
1=lane 0 in lock
Reserved, RO
xtxock<1> = lane 1 lock, RO
Reserved, RO,
1=lane 1 in lock
178
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