Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Serial Peripheral Controller (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SPI is a master on the
serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
• Three-wire serial port interface
• Full-duplex synchronous operation
• SPI bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test
Universal Serial Bus 2.0 (USB)
Two USB 2.0 interfaces provide both Device and Host support. These interfaces are provided as one USB 2.0 On-
The-Go (OTG) controller (Host and Device) and one USB 2.0 Host controller. Both controllers provide support to
an external PHY device through separate ULPI SDR interfaces.
Features include:
• USB 2.0 Host
– Fully compliant to the following specifications:
• Universal Serial Bus Specification, Revision 2.0
• Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0
• Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a
– One EHCI high speed (480Mbps) Host interface
– One OHCI full/low speed (12Mbps/1.5Mbps) Host interface
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Data and descriptor prefetch to optimize performance and off load CPU
– 4 KB buffer
• USB 2.0 OTG
– Fully compliant to the following specifications
• Universal Serial Bus Specification, Revision 2.0
• On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
– Configurable as a Host-only or Device-only controller
– Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transfers
– Maximum packet sizes of 1024B for isochronous transfers and 512B for bulk transfers
– Isochronous traffic can have three packets per microframe (196.6 Mbps throughput)
– Integrated DMA support to optimize performance and off load CPU
– Device support provides six Endpoints (3 IN, 3 OUT)
– 8192-byte FIFO by Endpoint (supports high-bandwidth isochronous transfers, double buffering of 1024-
byte packets)
– FIFOs are not shared between IN and OUT Endpoints
– Two USB 2.0 device Endpoints have DMA dedicated channels
– 16KB buffer
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AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
