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PPC460EX-SUB1000T 参数 Datasheet PDF下载

PPC460EX-SUB1000T图片预览
型号: PPC460EX-SUB1000T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 1000MHz, CMOS, PBGA728, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, MS-034, TEEBGA-728]
分类和应用: 时钟外围集成电路
文件页数/大小: 106 页 / 1089 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.19 – June 17, 2009  
460EX – PPC460EX Embedded Processor  
Preliminary Data Sheet  
DMA 4-Channel Controller  
The 4-channel DMA controller provides a DMA interface between the PLB memories and internal and external  
peripheral devices.  
Features include:  
• Supports the following transfers:  
– Memory-to-memory  
– Buffered peripheral to memory  
– Buffered memory to peripheral  
• Scatter/Gather capability for programming multiple DMA operations  
• 8-, 16-, 32-bit peripheral support (OPB and external)  
• 64-bit addressing  
• 128 byte FIFO buffer  
• Address increment or decrement  
• Support for:  
– Internal and external peripherals  
– Memory mapped peripherals  
– Peripherals running on slower frequency buses  
I2O/DMA Controller  
The I2O/DMA controller provides one High Speed DMA (HSDMA) interface to the PLB and support for I2O  
messaging. The HSDMA provides single-channel direct memory access support to ease the CPU burden. I2O  
manages Message Frame Address (MFA) FIFOs or queues in memory in response to I2O register reads and  
writes and transfers message frames.  
DMA features include:  
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)  
• Separate 512-byte buffering for transmit and receive  
– 1.4GB throughput (local read)  
– 1.0GB throughput (remote read)  
• Simultaneous fill and drain (PLB read/write pipelining)  
• Any source PLB address to any destination address  
• No memory alignment restrictions on source or destination  
• 32-byte command descriptor block  
• Maximum transfer size of 16MB  
• 64-bit addressing  
• Prefetch indicators for PCI buffer management  
• Supports initiation of transfer to the following address spaces:  
– Single beat I/O reads and writes  
– Single beat and burst memory reads and writes  
– Single beat configuration reads and writes (type 0 and type 1)  
– Single beat special cycles  
I2O features include:  
• I2O pull- and push-messaging methods  
• Dynamic message frame size  
• Programmable FIFO size (4096 64-bit MFAs maximum)  
• 64- and 32-bit MFA sizes  
• Three interrupt gathering methods  
• Registered MFA prefetch and posting  
• 32-bit inbound and outbound doorbell registers  
• Four 32-bit scratch pad registers  
18  
AMCC Proprietary  
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