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PPC460EX-SUB1000T 参数 Datasheet PDF下载

PPC460EX-SUB1000T图片预览
型号: PPC460EX-SUB1000T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 1000MHz, CMOS, PBGA728, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, MS-034, TEEBGA-728]
分类和应用: 时钟外围集成电路
文件页数/大小: 106 页 / 1089 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.19 – June 17, 2009  
460EX – PPC460EX Embedded Processor  
Preliminary Data Sheet  
Serial Ports (UART)  
The Universal Asynchronous Receiver/Transmitter (UART) interface provides one 8-signal port, or two 4-signal  
ports, or four 2-signal ports. The UART performs serial-to-parallel conversion on data received from a peripheral  
device or a modem, and parallel-to-serial conversion on data received from the processor.  
Features include:  
• Up to four ports in the following combinations:  
– One 8-pin (UART0)  
– Two 4-pin (UART0 and UART1)  
– Four 2-pin (UART0, UART1, UART2, and UART3)  
• Selectable internal or external serial clock to allow wide range of baud rates  
• Register compatibility with 16750 register set  
• Complete status reporting capability  
• Fully programmable serial-interface characteristics  
• Supports DMA using the 4-channel internal DMA function  
• 64-byte FIFOs for buffering transmit and receive data  
IIC Bus Controller  
The Inter-Integrated Circuit (IIC) interface provides a Philips® I2Ccompatible interface operating up to 400 kHz  
either as a master, a slave, or both, with a Bootstrap Controller (BSC) included. During chip reset, the Bootstrap  
Controller can read configuration data from an IIC-compatible memory device (for example, EEPROM). This data  
can be used to replace the default configuration settings provided by the chip.  
Features include:  
• Two IIC interfaces  
• Support for Philips Semiconductors I2C Specification, dated 1995  
• Operation at 100kHz or 400kHz  
• 8-bit data  
• 10- or 7-bit address  
• Slave transmitter and receiver  
• Master transmitter and receiver  
• Multiple bus masters  
• Supports fixed VDD IIC interface  
• Two independent 4 x 1 byte data buffers  
• Twelve memory-mapped, fully programmable configuration registers  
• One programmable interrupt request signal  
• Provides full management of all IIC bus protocols  
• Programmable error recovery  
• Port 0 includes an integrated BSC that supports a serial Bootstrap ROM with default override parameters at  
initialization  
AMCC Proprietary  
19  
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