Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
Serial ATA (SATA)
The Serial Advanced Technology Attachment (ATA) interface provides an interface to physical storage devices. It
shares the High-Speed SERDES with the PCI-Express interface with 1-Lane.
Features include:
• Compliant with Serial ATA Revision 2.5 Specification
• Supports SATA 1.5Gbps Generation 1 and 3Gbps Generation 2 speeds
• Supports device hot-plugging
• Supports power management
• Supports BIST loopback modes
• Dedicated DMA controller support to optimize performance and off load CPU
• Separate 512B transmit and receive buffers
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral
data bus.
Features include:
• One to four banks supported on EBC
• Direct interface to:
– Discrete NAND Flash devices (up to four devices)
– SmartMedia Card socket (22-pins)
• Device sizes of 4MB and larger supported for read/write access
• (512 + 16)-B or (2K + 64)-B page sizes supported
• Boot from NAND supported with execution of up to 4KB of boot code out of block 0
• ECC generation - hamming code, single-bit correction, double-bit detection (SEC/DED):
– ECC generation assist software with ECC checking of SLC NAND
– No ECC checking supported when booting directly from block 0
• Chip select pins are multiplexed with EBC
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor.
Features include:
• Time Base Counter (32 bits) driven by the OPB bus clock
• Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB bus
master accesses.
Features include:
• Sixty-four GPIOs multiplexed with other functions. DCRs control whether a GPIO pin acts as a GPIO or is used
for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
