Revision 1.19 – June 17, 2009
460EX – PPC460EX Embedded Processor
Preliminary Data Sheet
DDR2/1 SDRAM Memory Controller
The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard 184-pin DIMMs, SO-
DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing
modes are programmable. This controller interfaces to the PLB through a Memory Queue (MQ) function that
includes six high-speed 1KB FIFO buffers.
The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5V
and DDR2 devices require +1.8V.
Features include:
• Registered and non-registered industry standard DIMMs
• DDR2 333/400 support
• 64- and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 3.2GB/s peak bandwidth for the 64-bit interface
• 1.6GB/s peak bandwidth for the 32-bit interface
• Four chip (bank) select signals supporting four external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
bank)
• Up to 8GB in four external banks
• Up to two MemClkOut signals
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency and High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency and High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two 1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
16
AMCC Proprietary
Downloaded from DatasheetLib.com - datasheet search engine
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
