Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
Notes
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of
the frame reception (MII 0).
5V tolerant
3.3V LVTTL
PHY0RxDV[PHY0CrS1DV]
I
1, 5
or
Carrier sense data valid ([RMII 1])
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
5V tolerant
3.3V LVTTL
PHY0RxErr[PHY0Rx0Er]
PHY0TxClk[PHY0RefClk]
I
I
1, 5
1, 4
Transmit medium clock. This signal is generated the PHY
([MII 0]).
5V tolerant
or
3.3V LVTTL
Reference Clock [RMII and SMII].
Collision [receive error] signal from the PHY. This is an
asynchronous signal ([MII 1]).
5V tolerant
3.3V LVTTL
[PHY1Col][PHY1Rx3Er]
or
I
I
1, 5
1, 4
1, 4
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([RMII 3]).
Carrier Sense signal from the PHY. This is an asynchronous
signal ([MII 1]).
5V tolerant
3.3V LVTTL
[PHY1CrS][PHY1CrS2DV]
or
Carrier Sense Data Valid ([RMII 2]).
Receiver medium clock. This signal is generated by the PHY
([MII 1]).
5V tolerant
3.3V LVTTL
[PHY1RxClk]
I
i
Receive Data Valid ([MII 1]).
5V tolerant
3.3V LVTTL
[PHY1RxDV][PHY1CrS3DV]
or
Carrier Sense Data Valid ([RMII 3]).
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([MII 1][RMII 2]).
5V tolerant
3.3V LVTTL
[PHY1RxErr][PHY1Rx2Er]
[PHY1TxClk]
I
I
Transmit medium clock. This signal is generated the PHY
([MII 1]).
5V tolerant
3.3V LVTTL
SDRAM Interface
Memory Data bus
Notes:
MemAddr00:31
MemAddr12:00
I/O
O
3.3V LVTTL
3.3V LVTTL
1. MemAddr00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
BA1:0
RAS
Bank Address supporting up to 4 internal banks
Row Address Strobe.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
CAS
Column Address Strobe.
DQM for byte lane 0 (MemAddr00:7),
1 (MemAddr08:15),
DQM0:3
O
3.3V LVTTL
2 (MemData16:23), and
3 (MemData24:31)
46
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
