Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V PCI
PCIGnt1:5
PCIGnt1:5 output when internal arbiter is used.
O
HDLCEX Interface
HDLCEXTxClk
HDLCEXTxFS
Transmit Clock
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Transmit Frame Synchronization
Transmit Data port A
Transmit Data port B
Receive Clock
HDLCEXTxDataA
HDLCEXTxDataB
HDLCEXRxClk
HDLCEXRxFS
O
O
I
Receive Frame Synchronization
Receive Data port A
Receive Data port B
I
HDLCEXRxDataA
HDLCEXRxDataB
I
I
5V tolerant
3.3V LVTTL
[HDLCEXTxEnA]
[HDLCEXTxEnB]
Transmit Enable port A
Transmit Enable port B
O
O
5V tolerant
3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3
[HDLCMPTxClk4:7]
HDLCMPTxData0:3
[HDLCMPTxData4:7]
Transmit Clock signal that controls the transmit bit rate
Transmit Clock signal that controls the transmit bit rate
Transmit Data signal
O
O
O
O
3.3V LVTTL
5V tolerant
3.3V LVTTL
3.3V LVTTL
5V tolerant
3.3V LVTTL
Transmit Data signal
Transmit Data Enable signal that controls when the external
buffer is tri-stated
5V tolerant
3.3V LVTTL
[HDLCMPTxEn0:7]
HDLCMPRxClk0:3
[HDLCMPRxClk4:7]
HDLCMPRxData0:3
[HDLCMPRxData4:7]
O
I
Receive Clock signal that controls the receive bit rate
Receive Clock signal that controls the receive bit rate
Receive Data signal
3.3V LVTTL
5V tolerant
3.3V LVTTL
I
I
3.3V LVTTL
5V tolerant
3.3V LVTTL
Receive Data signal
I
Ethernet Interface
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with
respect to this clock (MII, RMII, and SMII).
EMC0MDClk
EMC0MDIO
O
3.3V LVTTL
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and SMII).
5V tolerant
3.3V LVTTL
I/O
1, 4
44
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
