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NPE405H-3BA266CZ 参数 Datasheet PDF下载

NPE405H-3BA266CZ图片预览
型号: NPE405H-3BA266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP NPe405H嵌入式处理器 [PowerNP NPe405H Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 70 页 / 1343 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.01 – April 18, 2007  
NPe405H – PowerNP NPe405H Embedded Processor  
Data Sheet  
Table 6. Signal Functional Description (Sheet 5 of 9)  
Notes:  
1. Receiver input has hysteresis.  
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.  
4. If not used, must pull up.  
5. If not used, must pull down.  
6. Strapping input during reset; pull up or pull down as required.  
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.  
Signal Name  
DQMCB  
ECC0:7  
Description  
DQM for ECC check bits.  
I/O  
O
Type  
Notes  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
3.3V LVTTL  
ECC check bits 0:7.  
I/O  
O
BankSel0:3  
WE  
Select up to four external SDRAM banks.  
Write Enable.  
O
ClkEn0:1  
SDRAM Clock Enable.  
O
Two copies of an SDRAM clock allows, in some cases,  
glueless SDRAM attachment without requiring this signal to  
be repowered by a PLL or zero-delay buffer.  
MemClkOut0:1  
External Slave Peripheral Bus Interface  
PerData00:31  
O
3.3V LVTTL  
External peripheral data bus when not in external master  
mode, otherwise used by external master.  
5V tolerant  
3.3V LVTTL  
I/O  
1
Note: PerData00 is the most significant bit (msb) on this bus.  
External peripheral address bus when not in external master  
mode, otherwise used by external master.  
5V tolerant  
3.3V LVTTL  
PerAddr00:31  
PerPar0:3  
I/O  
I/O  
1
1
5V tolerant  
3.3V LVTTL  
External peripheral byte parity signals.  
Peripheral write-bte enable. Byte-enables which are valid for  
an entire cycle or write-byte-enables which are valid for each  
byte on each data transfer, allowing partial word transactions.  
Used by either external bus controller or DMA controller  
depending upon the type of transfer involved. Used as inputs  
when external bus master owns the external interface.  
5V tolerant  
3.3V LVTTL  
PerWBE0:3  
[PerWE]  
I/O  
1, 2, 7  
Peripheral write enable. Low when any of the four PerWBE  
signals are low.  
5V tolerant  
3.3V LVTTL  
I/O  
O
7
PerCS0  
[PerCS1:7]  
5V tolerant  
3.3V LVTTL  
Peripheral Chip Selects  
Peripheral output enable. Used by either the external bus  
controller or the DMA controller depending upon the type of  
transfer involved. When the NPe405H is the bus master, it  
enables the peripherals to drive the bus.  
5V tolerant  
3.3V LVTTL  
PerOE  
O
7
1
Peripheral read/write. Used when not in external master mode  
by either the external bus controller or DMA controller  
depending upon the type of transfer involved. High indicates a  
read from memory, low indicates a write to memory.  
5V tolerant  
3.3V LVTTL  
PerR/W  
I/O  
Otherwise it used by the external master as an input to  
indicate the direction of transfer.  
5V tolerant  
3.3V LVTTL  
PerReady  
PerBLast  
PerClk  
Indicates peripheral is ready to transfer data.  
I
I/O  
O
I
1
Peripheral burst last. Used to indicate the last transfer of a  
memory access.  
5V tolerant  
3.3V LVTTL  
1, 7  
Peripheral Clock. Used by an external master and by  
synchronous peripheral slaves.  
5V tolerant  
3.3V LVTTL  
5V tolerant  
3.3V LVTTL  
PerErr  
Used to indicate errors from peripherals.  
1, 5  
AMCC Proprietary  
DS2011  
47  
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