Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
Table 6. Signal Functional Description (Sheet 8 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V LVTTL
UART1_Rx
UART1 Receive data.
UART1 Transmit data.
I
1
5V tolerant
3.3V LVTTL
UART1_Tx
[UART1_DCD]
[UART1_DSR]
[UART1_CTS]
[UART1_DTR]
[UART1_RTS]
[UART1_RI]
O
I
6
5V tolerant
3.3V LVTTL
UART1 Data Carrier Detect.
UART1 Data Set Ready.
1, 4
1, 4
1, 4
5V tolerant
3.3V LVTTL
I
5V tolerant
3.3V LVTTL
UART1 Clear To Send.
I
5V tolerant
3.3V LVTTL
UART1 Data Terminal Ready.
UART1 Request To Send.
UART1 Ring Indicator.
O
O
I
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
1, 4
1, 2
1, 2
5V tolerant
3.3V LVTTL
IICSCL[IECSCL]
IICSDA[IECSDA]
IIC [Initilization PROM] Serial Clock.
IIC [Initilization PROM] Serial Data.
I/O
I/O
5V tolerant
3.3V LVTTL
Interrupts Interface
5V tolerant
3.3V LVTTL
[IRQ0:6]
Interrupt Requests.
I
1
JTAG Interface
5V tolerant
3.3V LVTTL
TDI
TMS
TDO
TCK
TRST
Test Data In.
I
I
1, 4
1, 4
5V tolerant
3.3V LVTTL
Test Mode Select.
Test Data Out.
Test Clock.
5V tolerant
3.3V LVTTL
O
I
5V tolerant
3.3V LVTTL
1, 4
5
Test Reset. TRST must be low at power-on to reset the JTAG
boundary scan state machine.
5V tolerant
3.3V LVTTL
I
50
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
