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NPE405H-3BA266CZ 参数 Datasheet PDF下载

NPE405H-3BA266CZ图片预览
型号: NPE405H-3BA266CZ
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP NPe405H嵌入式处理器 [PowerNP NPe405H Embedded Processor]
分类和应用: 微控制器和处理器外围集成电路微处理器时钟
文件页数/大小: 70 页 / 1343 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.01 – April 18, 2007  
NPe405H – PowerNP NPe405H Embedded Processor  
Data Sheet  
Pull-up and Pull-down Resistors  
Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an  
appropriate state. The recommended pull-up value of 3kto +3.3V (10kto +5V can be used on 5V tolerant I/Os)  
and pull-down value of 1kto GND, applies only to individually terminated signals. To prevent possible damage to  
the device, I/Os capable of becoming outputs must never be tied together and terminated through a common  
resistor.  
If your system-level test methodology permits, input-only signals can be connected together and terminated  
through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that  
the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the  
NPe405H.  
Unused I/Os  
Strapping of some pins may be necessary when they are unused. Although the NPe405H requires only the pull-up  
and pull-down terminations as specified in the “Signal Functional Description” on page 43, good design practice is  
to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,  
and PCI buses should be configured and terminated as follows:  
Peripheral interface—PerAddr00:31, PerData00:31, and all of the control signals are driven by default. Ter-  
minate PerReady high and PerError low.  
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405H  
to actively drive all of the SDRAM address, data, and control signals.  
PCI—Configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and  
the remaining PCI control signals by doing the following:  
- Strap the NPe405H to disable the internal PCI arbiter.  
- Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kresistors to +3.3V.  
- Terminate PCIReq1:5 to +3.3V.  
- Terminate PCIReq0[Gnt] to GND.  
External Peripheral Bus Control Signals  
All external peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck,  
ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerNP NPe405H  
Embedded Processor User’s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float  
some of these control signals between transactions or when an external master owns the peripheral bus. As a  
result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices  
receiving that particular signal.  
The following table lists all of the I/O signals provided by the NPe405H. Please see “Signals Listed Alphabetically”  
on page 15 for the pin number to which each signal is assigned. In cases where a multiplexed signal (indicated by  
the square brackets) is shown without the other signals that are assigned to that pin, you can see what the other  
signals are by referring to the same table.  
42  
DS2011  
AMCC Proprietary  
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